There are high expectations for SiC as a next-generation power semiconductor device material. SiC is about three times as high in band gap, about ten times as high in breakdown field strength and about three times as high in thermal conductivity as Si, and has good physical properties as a power semiconductor device material. The use of such physical properties makes it possible to obtain a power semiconductor device enabling far lower loss than an Si power semiconductor device, as well as high-temperature operation.
While there are various high breakdown voltage semiconductor devices using the characteristics of SiC, a double implantation MOSFET (hereinafter referred to as a DIMOSFET), for example, is known in which a p-well and a source region are formed by ion implantation. The DIMOSFET is easy to manufacture because it uses a planar process, which enables more accurate channel formation by an ion implantation method. Moreover, the DIMOSFET allows a drive circuit of lower power because gate driving is performed by voltage control, and the DIMOSFET is therefore a good device suitable for parallel operation as well.
However, the DIMOSFET has the following problems. An n-type source region of the SiC-DIMOSFET is generally formed by high-dose ion implantation with nitrogen or phosphorus which is then thermally treated for activation at about 1600° C. At this point, the ion implantation is carried out under a high-dose condition up to the surface of SiC in a box profile, and the thermal treatment at a high temperature of about 1600° C. is used, which leads to considerable damage to an ion-implanted region of the SiC surface. As a result, a priority sublimation phenomenon of Si occurs starting from the implantation region. This causes surface roughening on the source region for 10 nm or more, and then, when a gate dielectric is formed over the source region and a p-type base region by, for example, a thermal oxidation method or a CVD method, the surface roughening on the source region is directly reflected on the gate dielectric on the source region. This leads to a significant decrease in the breakdown voltage, breakdown yield and long-term electrical reliability of the gate dielectric.
Although it is generally said that the surface roughening on the source region is reduced in the case of nitrogen ion implantation, it has been reported that surface roughness increases with a high ion implantation concentration even in the case of nitrogen and the breakdown yield decreases (refer to Junji Senzaki et al., ICSCRM2007, Mo-P-68). Moreover, it has also been reported that a new crystal defect could be induced by nitrogen implantation and activation annealing (refer to M. Nagano et al., ICSCRM2007, Mo-P-14).
In order to solve the problem of the ion implantation, a double epitaxial MOSFET (DEMOSFET) in which a p-type base region (well) is formed by an epitaxially formed film alone has been reported. However, the above-mentioned method utilizes epitaxial growth which requires a long time for a manufacturing process.
As described above, the problems with the conventional DIMOSFET are that surface roughening is caused on the source region due to the high-temperature thermal treatment after the phosphorus or nitrogen ion implantation, and when the gate dielectric is then formed, the surface roughening on the source region is directly reflected on the gate dielectric on the source region, leading to a significant decrease in the breakdown voltage, breakdown yield and long-term electrical reliability of the gate dielectric.
Although the DEMOSFET in which the p-type base region (well) is formed by the epitaxially formed film alone has been reported to solve the above-mentioned problem, this method utilizes epitaxial growth, which requires a long time for the manufacturing process.
Therefore, there has been a desire to obtain a silicon carbide semiconductor device capable of reducing the process time, capable of high performance with extremely low on-resistance using physical properties intrinsic in SiC and capable of greatly improving the breakdown voltage, breakdown yield and long-term reliability of the gate dielectric.